1. Field of the Invention
The present invention relates generally to level shifters for interfacing independent power domains, and more particularly, to multiple function and configurable level shifters for shifting signals to compatible voltage levels between domain crossings in systems with multiple power domains.
2. Description of the Related Art
In order to optimize the trade-off between speed and power consumption, many electronic circuits include multiple independent power domains. Power domains are differentiated by a variance between a voltage level of a power source, such as a difference in voltage level between a ground or reference voltage level, generally referred to as “VSS”, or a difference in voltage level between a source voltage level, generally referred to as “VDD.” Power domains may alternatively be referred to as voltage domains which operate within different voltage levels. A level shifter may be provided at an interface or “crossing” between separate or otherwise independent power domains so that a signal asserted by one power domain operating at one voltage level is level shifted and driven to a different voltage level compatible with another power domain. As used herein, each signal is generally considered a digital or a binary signal which is switched between opposite logic levels, such as logic one (1) and logic zero (0). Also, the signals described herein and shown in the Figures, including voltage supply signals, input signals, output signals, etc., are developed on corresponding nodes with the same name unless otherwise specified. Each logic level is determined relative to a specific voltage level, so that it is desired that the signals are switched within voltage levels that are compatible with the power domain receiving the signal. Otherwise, an incompatible binary signal may be misinterpreted which could lead to an incorrect result which may lead to improper operation or even operation malfunction.
The operative voltage level of a given power domain may be modified when the power domain is placed into a different operating mode, such as any one of several power-conserving modes (e.g., standby, sleep, hibernation, etc.). A level shifter with bypass may be used to bypass voltage level shifting when the voltage level between two domains are equal or otherwise become equal. A level shifter may be implemented with isolation, such as an isolation cell or the like, to drive an output of a powered-down domain to a known logic level provided to an input of a domain which remains powered-up.
For some technology nodes, significant reductions in leakage and power consumption can be obtained by back biasing transistor devices, provided that the circuitry is operated at a lower frequency. Back biasing generally involves driving a voltage differential between the bulk or substrate of a device and the gate of the device. In a standard complementary metal-oxide semiconductor (CMOS) configuration, the source and substrate of P-channel MOS (PMOS) devices are both tied to VDD and the source and substrate of N-channel MOS (NMOS) devices are both tied to VSS. In one conventional back biased CMOS configuration, the bodies of PMOS devices are pulled to a voltage above VDD and the substrates of NMOS devices are pulled to a voltage below VSS. Since VSS is typically defined at zero (0) Volts (V) or ground, a charge pump or the like is used to drive the substrate of NMOS devices to a negative voltage level below ground. One disadvantage with the conventional back bias approach is the use of a relatively low efficiency charge pump or the like which increases overall power consumption. Another disadvantage is the corresponding increase of the overall voltage swing. Such back bias approach is particularly disadvantageous for battery-powered electronic devices with limited overall voltage range.
An alternative back biasing technique is referred to herein as “source biasing,” in which the substrate of NMOS devices are held or otherwise tied to ground and the voltage level of VSS is increased, which increases the voltage level of the source terminals of NMOS devices. There is generally sufficient headroom even in battery-powered devices to drive the substrates of P-type devices above VDD so that the overall voltage range is not appreciably affected. The source biasing technique may result, however, in power domains operating at different ground potentials in some power modes. If the power domains were also operated with different VDD source voltages, a power level-shifter and a ground level-shifter were both needed to level shift the signal for both power and ground levels. The use of multiple level-shifting cells, however, was error-prone and caused additional delays.
The industry would benefit from the availability of level shifters that cross both source voltage and ground domains, that minimize delays by bypassing level shifting when appropriate, and that provides built-isolation if desired.